The present invention relates to isolation regions used in semiconductor integrated circuits, and in particular to the formation of a shallow trench isolation structure.
The trend in semiconductor integrated circuits is to increase the density of the number of devices in a silicon substrate area. The density is dependent on not only the area of the device, but on the area required to separate or isolate one device from another. Increased density is particularly advantageous in, for example, non-volatile memory devices, such as erasable and electrically programmable read-only memory (EPROM) cells; electrically, erasable programmable read-only memory (EEPROM) cells; and Flash EEPROM cells useful in memory arrays and programmable logic devices.
Isolation regions, such as shallow trench isolation (STI) structures, are used commonly in the semiconductor industry to prevent parasitic channels between adjacent devices. STI is advantageous because fine trenches can be formed thereby reducing the isolation area and increasing density.
FIG. 1 shows a conventional method of forming a STI structure that is used, e.g., in a Flash memory device. FIG. 1 shows a silicon substrate 10 with a STI region 12. STI region 12 includes a trench 14 that is lined with a thermal oxide layer 16. The trench 14 is filled with a TEOS (tetra-ethyl-orotho-silicate) layer 18. The TEOS layer 18 is generally applied to a thickness so that the top of the TEOS layer 18 is about the same level as the top of a nitride layer (not shown). The nitride layer and an underlying oxide layer are then stripped off, leaving the top of TEOS layer 18 higher than silicon substrate 10. A polycrystalline silicon (polysilicon) layer 20 is then deposited over TEOS layer 18 and silicon substrate 10.
As shown in FIG. 1, a seam 22 is produced in TEOS layer 18. Unfortunately, when polysilicon layer 20 is deposited over STI region 12, seam 22 is filled with polysilicon, which leads to interpolysilicon shorts and creates leakage.
The polysilicon layer 20 is then covered with a photoresist (not shown) which is patterned. The patterned photoresist and underlying polysilicon is etched away resulting in the structure shown in FIG. 2. As can be seen in FIG. 2, polysilicon layer 20 is patterned with space 24. Because polysilicon layer 20 is conventionally etched in an anisotropic etch process, a space 24 that is less than 0.2 xcexcm is difficult to define.
Moreover, polysilicon layer 20 has large step heights, as shown in FIGS. 1 and 2. Thus, subsequent processing steps may have problems with material not completely etching off the sidewalls, i.e., stringers, which may lead to shorts.
Thus, what is needed is a STI structure that may be used in a densely packed array, such as in Flash memory, and that will eliminate problems associated with interpolysilicon shorts, stringers, and may easily define small spaces in the polysilicon layer overlaying the STI region.
In accordance with an embodiment of the present invention, a semiconductor device, such as Flash memory, includes a STI region in a substrate. After removing the pad oxide and nitride layers over the substrate, a nitride layer is deposited. The nitride layer is patterned and etched to produce a nitride spacer, for example, above the STI region. Advantageously, nitride from the nitride layer will fill any seams present in the dielectric layer of the STI, thereby reducing leakage. A polysilicon layer is deposited and etched back to the top of the nitride spacer. Thus, the polysilicon layer is formed with an approximately planar topology, thereby reducing stringers in subsequent processing. The nitride spacer is then etched away leaving a space in the polysilicon layer. Because a nitride spacer is used to define the size of the space in the polysilicon layer, a small space may be easily produced.
Thus, an apparatus, such as a Flash memory is produced that includes a substrate with a STI region. The STI region includes a dielectric layer with a seam, which is filled with nitride. At least a portion of the STI region is covered with a polysilicon layer having a top surface that is approximately planar. The polysilicon layer may have an opening over the STI region.